客户：半导体行业巨头的子公司，在中国上海等地有开设分店。
有意者请发送简历至
[email protected]或者介绍你觉得可能合适的人给我发邮件。谢谢！
Requirements
PhD/Masters/Degree in Electrical/Electronics Engineering
Minimum five years experience in Design for Test (DFT) of olarge, lower geometry SOC design.
Experience in DFT concepts, test mode and power management during test.
Good knowledge in Boundary Scan, ATPG Scan, at_speed scan, and MBIST is a must.
Experience with industry standards tools for DFT and Verification
Knowledge in complete design flow, including STA and timing analysis will be added advantage.
Proficiency in VHDL/Verilog and high level programming languages “C”, “C++”, Perl and script writing.
Experience in Test Development and Product Engineering will be an added advantage
Experience in analog DFT is of added advantage
Understanding of structural test concepts of digital designs is required
Team Player with an open and co-operative personality
Responsibilities
Definition/generation of Design for Test (DFT), Design for Analyzability(DFA), Design for Manufacturability(DFM) concept
Development, implementation and verification of DFT/DFA measures (standard DFT measures as well as project specific non-standard DFT measures).
Test mode definition/ documentation/ implementation/ verification.
Test pattern generation/ verification.
Achieve target structural test coverage and test time
Development of new DFT methods/ features to increase test coverage at reduced test cost
Increase DFT knowledge base, drive know-how exchange across projects and other locations world wide.