TD-ThinFilm Senior Engineer
Position Title: TD-ThinFilm Senior Engineer
Location : Singapore


Responsibilities:
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To develop, sustain and improve process to meet technology development goals

Startup and qualify new tool and process

Optimize and develop process by using SPC and DOE knowledge

Establish SOP, CAS and FMEA for Fab operation

Conduct process training to AE / Snr AE / Engineer

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Requirements
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Degree, Masters in Engineering

Acquire strong knowledge on hardware configuration and understand related process issue

Basic integration knowledge

Deep knowledge and strong problem solving skill on responsible process

Able to drive process CIP to improve process performance indices

Honest, confident, and self motivated

Teamwork and cross-team collaboration

Taking ownership and proactively drive process optimization to its excellent



We regret that only shortlisted candidates will be notified.

Senior Engineer - eSRAM
Position Title: Senior Engineer - eSRAM
Location: Singapore


Responsibilities:
~~~~~~~~~~~~~~~~~~~~~~~~~

Process integration for 65nm and below technologies development

Key emphasis on memory (SRAM, Non-volatile, eDRAM) technology development

To integrate new processes throughout development and qualification phases, with emphasis on memory related areas, to meet technology release requirements

To work with different teams (process module, device, product & fab operation) to develop and qualify memories and/or eFuse on new processes

To design bitcell, integrate, design and draw test structures, define new ET and inline specs for memories and/or eFuses for new process and technology during development phase

Assist with transfer of new memories and eFuses to fab

To perform data analysis and problem solving for ET and yield on memory and/or eFuse related items

To be able to understand design rules, generation rules and tapeout process flow

To be able to perform tapeout activities (TSRF, PTRF, jobviews, etc) with emphasis on memory and/or eFuse

Provide technical expertise in memory and/or eFuse technologies


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Requirements
~~~~~~~~~~~~~~~~~~~~~~~

Bc/MS/PhD Engineering or Sciences;

Knowledge of device physics and CMOS process integration

Minimum 2+ years as process integration engineer

Semiconductor foundry process integration knowledge

CMOS device knowledge

Memory related (SRAM, Non-volatile, eDRAM) technology knowledge

Semiconductor device, test-key, circuit layout knowledge

Understanding of semiconductor memory and/or eFuse technologies

DC parametric measurements on HP ET testers

Wafer inspection experience

Knowledge of Process Flow/Runsheet Integration

ET & Data Analysis experience

Understanding SPC and FA techniques

Problem Solving Skills

MS application skills (Word, Excel, etc)

Basic PC/window skills

Good communication & interpersonal skills

Demonstrate ownership of the assignment given

Strong motivation in self-learning

Able to work independently or as a team

Senior Engineer - BiCMOS (200mm)
Position Title: Senior Engineer - BiCMOS (200mm)
Location: Singapore



Responsibilities:
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Own key customers and process development lots

Co-ordination of unit process experiments/development

Supporting process/device debugging

Support process/device-testing methodology/techniques

Cross-checking and auditing data analysis/reports by AE’s/Engineers

Development phase Device /Process characterization

Support prototype’s technical logistics & execution

To own process development and customer’s prototype lots and ensure smooth & correct execution

To be responsible for device (CMOS, BJT and passive)/process problem debugging

To set-up Bipolar/CMOS/passive device/process testing methodologies and techniques

To carry out short loop and full loop experiments to develop high performances bipolar and/or MOS devices

To characterize all active (Bipolar transistors, MOS transistors, diodes, varactors) and passive devices (Resistors, capacitors, inductors etc.) in the process development phase

Do be responsible for new process step wafer inspection and new development step defect finding

To support prototype technical support like MEBES job-view, frame cell checking and correct process ID/Bias table/recipe usage


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Requirements
~~~~~~~~~~~~~~~~~~~~~~~~~~

Degree/Masters/PhD in Electrical / Electronics Engineering or equivalent

2-4 year’s relevant experience in BiCMOS process development, device design & debugging in manufacturing environment

Device physics knowledge is essential

Good interpersonal skill, tactful, resourceful, good aptitude of DOE, continuous learning attitude

TD - CMP Senior Engineer/Engineer
Position Title: TD - CMP Senior Engineer/Engineer
Location: Singapore


Responsibilities:
~~~~~~~~~~~~~~~~~~~~~~~~


CMP process developments and qualifications for leading edge technologies

CMP process improvement for yield enhancement and cost reduction

Trouble-shooting and issue debugging

Routine tool setup and process control

Production line support


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Requirements
~~~~~~~~~~~~~~~~~~~~~~

Masters in Chemistry or chemical engineering, Materials science and engineering, physics, Mechanical & Production Engineering, Electrical Engineering

2 years relevant experience

Hardworking

Can work under stress

TD - Diffusion Snr Engineer/Engineer
Position Title: TD - Diffusion Snr Engineer/Engineer
Location: Singapore



Responsibilities:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


To develop and characterize reliable and manufacturable unit module processes which meets overall integration requirements with sufficient manufacturing processing windows

Develop robust diffusion baseline processes

Process transfer (inter-fab or inter-devision) with good process matching

Responsible of continuous improvement of baseline process such as particle reduction and CPK improvement

Work with equipment team on process improvement, process characterization of process for both Single Wafer and Batch tools.

Utilize DOE techniques to optimize process windows

Develop new unit processes and Prepare reports for all new unit process development and improvement and make recommendation of the best-known recipe for the corresponding technology

Participate in new equipment or new materials selection and responsible for filing of associated documents

Participate in relevant cross functional activities, such as misc Task Force activities


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Requirements
~~~~~~~~~~~~~~~~~~~~~~~

Master in Electrical/Electronics/Chemical/Microelectronics Engineering/Physics/Material Science

Knowledge on Semiconductor preferred

Knowledge on SPCView; Process control Method

Knowledge on VAS Technology (e.g. Memory chips, and etc)

Be upright, open, honest, truthful and constructive

Customer orientation

Constant self-development to broaden technical bandwidth including equipment engineering familiarisation

Constant challenge of status quo

Dedication and commitment to company and job

Resolve and ability to fulfill commitment

Display proactivity and initiative

Taking ownership, being accountable and ability to get things done

Willingness to accept assignments

Teamwork and cross-team collaboration

Proven technical abilities in problem analysis and problem-solving skills in process engineering

Senior Engineer/Engineer (TCAD)(fresh graduate can apply)
Position Title: Senior Engineer/Engineer (TCAD)
Location: Singapore


Responsibilities:
~~~~~~~~~~~~~~~~~~~~


Optimize CMOS and Bipolar process and device using TCAD simulations

Accelerate technology development and technology transfer using TCAD software for process and device simulations

Work closely with R&D device and process integration teams to evaluate physical and electrical experimental data

Work closely with Fab process integration teams to match device and process to customer needs

Optimize process and device stability control using DOE (Design Of Experiments) and DFM (Design For Manufacturability) methodologies

Create and monitor timelines and plans for TCAD development work

Generate methodologies for continuous improvement of TCAD calibration and simulations


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Requirements
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


Degree in Material Science, Physics or Chemistry with microelectronics module or experience

3 or more years of relevant fab experience preferred

Good interpersonal and communication skills

Good analytical skills/presentation skills

Essential in using MS Office/UNIX/LINUX and familiar with SUN and PC environment

Good in using Tsuprem4,Medici,TWB as well as Sentaurus Process and Device and Sentaurus WorkBench

Must be a team player and capable to adapt quickly to new environment

New graduate with suitable background and education or more years in Academic Institution with or without industrial experience can be considered

Senior Engineer / Engineer (eFlash)
Position Title: Senior Engineer / Engineer (eFlash)
Location: Singapore


Responsibilities:
~~~~~~~~~~~~~~~~~~~~~~~


Device characterization & analysis.


Develop integration solution for NVM processes


Analyse inline & electrical test data for process & yield improvement.


Work with process engineering on process & yield improvement


Work with device & product engineering on process & yield improvement


Drive for NVM performance improvement on endurance & retention


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Requirements
~~~~~~~~~~~~~~~~~~~~~~~~~~


Degree/Masters/PhD in Electrical or Electronics Engineering or Physics or equivalent


>3- 6 years’ process integration, flash technology experience or device engineering background


NVM process development & integration experience.


NVM characterization & product testing knowledge


NVM technology device & product qualification experience.


CMOS process integration experience


Device physics, product or yield engineering


Experience in prototyping activity.


Cross-functional working personality.


Proactive on problem solving

Senior Engineer -RFCMOS
Position Title: Senior Engineer -RFCMOS
Location: Singapore



Responsibilities:
~~~~~~~~~~~~~~~~~~~~~~~


65nm/55nm/40nm/28nm RF device and testchip layout and tapeout

Customer's proto tapeout: Frame, SLM DUTs, Crackstop, customize testchip and test structures

65nm HV device and testchip layout and tapeout

Execute Tapeout requirement, such as PTRF, DRC, MEBES review etc

Increasing RF tech nodes: 65LPe, 55nm, 40nm & 28nm, to deliver

Increasing 65LPe RF customers' tapeout to support

To develop and setup 65nm HV by end 2011.

To kick-start test chip development ASAP


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Requirements
~~~~~~~~~~~~~~~~~~~~~~~~

B.S. Degree (M.S. is preferred) in Electrical Engineering, Computer Science or other relevant engineering discipline is required

Attention to detail

Patient, resourceful, tactful

Good interpersonal skill

Continuous learning attitude

RFCMOS Engineer
Position Title: RFCMOS Engineer
Location: Singapore



Responsibilities:
~~~~~~~~~~~~~~~~~~~~~~~~~~~


Support on LDMOS and or HV development on for the following:

Device characterization measurement, analysis, investigation and report documentation

Device test structure layout

Running engineering lots



Engineering split execution

Standard step inline wafer inspections

Own lots while learning the process development

Failure analysis & reliability testing co-ordination

Execute Tapeout requirement, such as PTRF, DRC, MEBES review etc


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Requirements
~~~~~~~~~~~~~~~~~~~~


Masters Degree in Engineering

Know Semiconductor Physics and or devices

Know bench measurement

Good interpersonal skill, tactful, resourceful, continuous learning attitude

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GLOBALFOUNDRIES Fast Facts

Locations:

■Headquartered in Silicon Valley
■Manufacturing Centers in Germany, Singapore and New York
■Regional Sales and Support Offices in Shanghai, Yokohama, Hsinchu, Austin, London, Munich

Capacity

■Five 200mm fabs and two 300mm fabs in production, one 300mm fab under construction
■Total capacity in 300mm and 200mm wafers is expanding to 7.7 million 200mm equivalent wafers, as described below.
Expanding to 2.3 million 300mm wafers annually
Installed base of 2.2 million 200mm wafers annually, expanding to 2.5 million

Employees:

■Approximately 10,000 employees
■Spanning three continents across 12 locations

Revenue:

■$2.5B US in 2009
■One of the world's largest semiconductor foundries by revenue

Customers:

■Over 150 worldwide
■Includes many of the world's largest semiconductor companies

Capital Expenditure Plans:

■$6B US committed for future expansion
■Fab 8 in Saratoga County, New York is currently the largest commercial capital expansion project in the USA