word 附件好像传不上，贴内容如下。
Cadence www.cadence.com 是全球领先的EDA (Electronic Design Automation) 软件开发商以及电子设计自动化解决方案提供商.我们的产品涵盖了电子设计的整个流程，包括系统级设计，功能验证，IC综合及布局布线，模拟、混合信号及射频IC设计，全定制集成电路设计，IC物理验证，PCB设计和硬件仿真建模等。全球知名半导体与电子系统公司均将Cadence软件作为其全球设计的标准。
Cadence在中国有2个研发中心，上海研发中心成立于2005年12月, 是Cadence全球最具成长性的研发中心，承担数字芯片设计，系统设计等各方面先进电子设计自动化工具的研发任务。目前我们的上海研发中心位于张江高科技园区碧波路690号张江微电子港8号楼，有研发人员近200人。
Cadence北京研发中心 成立于2003年, 现位于海淀区海淀东三街2号欧美汇大厦，主要协同美国总部共同研发Virtuoso全定制设计平台及其多模式仿真 (multi-mode simulation) 产品。 Virtuoso全定制设计平台是用于快速、硅精度设计的综合系统。Virtuoso平台包括：业界唯一的规格驱动的环境；使用通用语法、模型和方程式的多模式仿真；快速版图设计，用于0.18微米以下工艺的先进硅分析和全芯片混合信号集成仿真环境。使用该平台，设计团队可以用从1微米到45纳米的工艺迅速、准确、按时地设计出硅片.
我们正在上海和北京寻找软件研发工程师和产品测试工程师，同时 有多个实习生职位空缺，欢迎微电子，电子，计算机，软件工程，物理，数学及相关专业应届毕业硕士/博士加入我们！
如有兴趣请投递简历至 [email protected]，并标注你申请的职位名称。
对职位有任何疑问，也可发邮件至该信箱，我们HR同事会及时给你回复并尽快安排面试。
R&D- Shanghai
Senior Software Engineer of Power Route (Location: SH)
Position Requirements
This position is for a R&D engineer to assist in development of special routing (power planning / power routing ...) solution of digital IC design in Encounter.
The candidate will be responsible for designing, developing, troubleshooting and debugging software programs of routing flow and related algorithms.
Position Requirements
The candidates should have strong software programming skill with C/C++ on Linux/Unix platform.
Strong desires to learn and explore new technologies and is able to demonstrate good analysis and problem solving skills
EDA software development experience or IC design knowledge, especially in backend
Know basic routing algorithms.
Good English communication skill, both oral and written.
Senior Software Engineer for 3D IC (Location: SH)
Position Description:
The candidate will be responsible for designing, developing and debugging software programs of 3D IC/TSV.
Position Requirements:
Strong C/C++ programming skill on Unix platform.
Experience with physical design is a plus.
Familiar with graph algorithm.
Senior Software Engineer for Modeling (Location: SH)
Position Description
Seeking software engineer to develop and debug software addressing Design for Manufacturability (e.g., lithography, CMP)
Position Requirements
Candidate must be familiar with software engineering methods and committed to high quality of development work. The individual must be team-oriented, possess good communication skills, self-motivated, able to work independently and working with a team from multiple remote sites. Candidate must be able to develop detailed technical specification as well as the ability to scope efforts required.
B.S. In CS, EE, or equivalent fields with competency in object-oriented language programming
Strong analytical skills, systematic thinking, and problem-solving minded; can work creatively and independently on a larger scale problem set
Industry experience in programming or PE (scripting) work related to geometry-based signoff tools such as DRC and RCE
Exposure to lithography and/or CMP technology, lithography-related and/or CMP EDA tools is preferable
Senior Engineer for Emulation Runtime Software (Location: SH)
Position Description
Software engineer working in a team oriented environment to develop and maintain advanced emulation and co-simulation runtime software tools. Responsibilities include working on emulation and co-simulation runtime command interface, GUI tools development, run control software/firmware interface design and integration, and various runtime software modules for existing and future generation emulation system.
Position Requirements
Bachelor or Master Degree in EE/CS/CE
C/C++, Tcl/Tk and Unix shell programming skills. Prefer with Multi-threading, RPC and Socket programming experience.
Knowledges with Verilog or VHDL design language and logic design.
EDA/CAD tool development experience or logic design verification experience.
Good communication skills (prefer English language proficiency), attention to details, and ability to work in multi-site/multi-person project.
Lead PV Engineer(Location: SH)
Position Description
We are looking for an engineer/designer with the desire to perform product validation on our Signal Integrity products. You will be responsible for testing and overseeing the quality management of our family of software products that deal with high speed signal design.
Duties include working within a multi-functional global project team, review and develop automated tests within the existing test environment, review project plans and functional specifications, develop test criteria and written test plans, manually exercise and test functionality of the Allegro SI product.
Position Requirements
B.S. degree or above
Knowledge in Signal Integrity analysis, such as Bus Analysis, SSN, Crosstalk and Power Analysis.
English are mandatory as the candidate will be interacting with a global team.
Excellent debugging skill
Knowledge of Cadence Allegro platform is a plus
Knowledge of other high speed tools is a plus
Knowledge in Printed Circuit Board design is a plus
Experience with Perl, Java or other programming languages is a plus
Familiar with UNIX and Window systems
Senior FPGA Engineer
Position Description
Responsible for designing and developing sub-systems and modules or components of hardware based verification products. In addition modifying, updating and productizing existing hardware based verification products. Perform as individual contributor on FPGA based design projects involving board design, RTL design, verification, productizing and documentation. Work on diverse problems related to FPGA design, simulation or verification issues.
Position Requirements
The position requires BSEE, or equivalent, with experience in designing hardware systems.
Must have excellent communication skills, both written and verbal.
Technical expertise in FPGA design for either Altera or Xilinx products is required.
Experience in FPGA design methodologies including high speed design, serial protocols and FPGA timing closure is desired.
In addition RTL design knowledge using Verilog is required along with experience in using RTL verification tools and flows.
Verification using Cadence simulation products is desired.
Experience with scripting languages like Perl, TCL C-shell is strongly recommended.
Experience with PCB tools is also desired. Experience with high speed memory interface design is also desired.
Senior Software Engineer for SPB
Position Description:
The candidate will be a member of the SPB R&D team in HSTC, Shanghai, to work on the development and maintenance of high-speed projects.
The responsibilities include the develop of new features and products, and support other team member in SPB high-speed product lines.
The candidate must be comfortable working with existing code as well as developing new functionality to address new requirements, and be working closely with local/remote team members, and be also strong technical support to team.
Position Requirements:
Candidate must be an expert in software engineering methods and committed to high quality of development work.
The individual must be team-oriented, possess good communication skills, self-motivated, able to work independently and working with a team from multiple remote sites.
Candidate must be able to develop detailed technical specification as well as the ability to scope efforts required.
The candidate must be also smart to capture new EDA technologies, and switch among different areas successfully.
Advanced developing and debugging software in Windows, UNIX & LINUX environments, including the C/C++ and VC .net programming and GUI design.
Strong problem-solving, architecture, algorithmic, and GUI development abilities are a must.
Familiar with interpreted language such as SKILL is a plus.
Knowledge of SPB design tools such as: Layout Editor, Schematic Editor, Modeling and Measurement are also a plus.
Product Verification Engineer- Shanghai
1. Sr. PV Engineer for Encounter QOR (Location: SH)
Position Description
This job is an important addition to our R&D team to develop CIC tool.
Responsible for developing, applying, and maintaining quality CIC product.
Required to acquire expertise and ownership over existing product components as well as develop entirely new product features.
Work with other engineers as a team and help to provide feedback when required.
Position Requirement
MS with EE background, from design house or EDA Company or fab is strong plus. Excellent new graduate can be considered.
Be familiar with software development process, debugging tools, and configuration management concepts.
Prior experience and education in APR is a plus.
Candidate must have excellent ability to learn, explore and solve problems, have team-cooperating and innovating spirit
Candidate must possess good Chinese and English communication skills;
3. Senior PV Engineer (Location: SH)
Position Description
This job is an important position for our regression system infrastructure.
Responsible for applying and maintaining the regression system, also responsible for next generation regression system development, including the auto launch, regression gate system, NEW new launching engine and the interface with our data base.
Position Requirements
MS background. Excellent new graduate can be considered.
Be familiar with software development process, good at perl, csh, tcl and have basic knowledge about system level scripting development.
Candidate must have excellent ability to learn, explore and solve problems, have team-cooperating and innovating spirit,
Candidate must possess good Chinese and English communication skills;
4. Senior PV Engineer for PVS (Location: SH)
Position Description
This job is an important addition to our R&D team to develop PVS.
Responsible for developing, applying, and maintaining quality standard for PVS related technology and products.
Responsible for testing PVS in all kind of Virtuoso/Encounter/K2 design flow.
Required to acquire expertise and ownership over existing product components as well as develop entirely new product features.
Work with other engineers as a team and help to provide feedback when required.
Position Requirements
Master degree with EE background, from design house or EDA Company or fab is strong plus. Excellent new graduate can also be considered.
Prior experience in Physical verification is desired. Be good at usage of mainstream Cadence/Synopsys/Mentor Assura, Hercules, Calibre tools.
Be familiar with software development process, debugging tools, and configuration management concepts is a plus.
Candidate must have excellent ability to learn, explore and solve problems, have team-cooperating and innovating spirit,
Candidate must possess good Chinese and English communication skills;
Intern- Shanghai
PV(产品验证/测试) Intern for Regression system development
Position Description
Need 4 days/week or full time over 6 months working with PV regression team for daily yellow and full QA review
Help PV team deliver some system scripts (by perl/csh)
Requirement:
MS or excellent undergraduate, good at programming, especially for perl, csh.
Should understand data base & the concept about regression testing.
Good communication in English and Chinese, good confidence and good self-motivation.
PV(产品验证/测试) Intern for STA
Position description:
This intern will work in Encounter Common Timing Engine Product Validation team. The responsibilities include:
a) Assist in Cadence STA product and engine's developement and validation
b) validate comprehensive STA testcases for Encounter Digital Impelementation System and Encoutner Tming System
c) Develope and maintain system and infrastructure for high productivity and efficiency with various scripting and system developement techniques
Requirement:
MS or excellent undergraduate, Strong perl programming experience.
IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus
Unix System knowledge, vi/TCL/TK/CSH will be plus
Good communication in English and Chinese, good confidence and good self-motivation.
Commitment to work as intern at least 4 days per week for more than 6 months
R&D Intern for Infrastructure (Location: SH)
Position Description:
The candidate will be responsible for maintaining components software for Encounter platform of Cadence and work as gate keeper of RD code for daily quality check.
Position Requirements:
BS/MS candidate in CS/EE/ Mathematics or related area.
Be Familiar with C/C++ programming.
Be Familiar with script language, such as csh or perl.
Be Familiar with programming on Linux/Unix platform.
One or more items of the following skills are plus.
Be Familiar with GUI application development, such as Qt, tcl/tk, X.
IC design background.
EDA software development experience.
Good English communication skill, both oral and written.
Team player.
Beijing R&D
Senior Developer(Location: BJ)
Position Description:
The positions are for a developer who will be responsible for designing, implementing, and maintaining library characterization and validation software for use with standard cells, memory and macro blocks, and IO cells.
Requirements:
The candidates should have experiences in developing EDA software.
Must be proficient in C, C++, TCL, and development in Linux/Unix.
Knowledge on semiconductor device is strong plus.
Experience with SPICE or SPICE-like circuit simulation is important.
Knowledge of Verilog and VHDL is also highly desirable.
The ideal candidate would have a good understanding of library characterization, IP design, static timing analysis, power analysis, and signal integrity analysis flows.
Minimum Education Required / Minimum Experience Required : Master or Ph.D. in MS, EE, CS, Math or Physics
Product Verification Engineer(Location: BJ)
Position Description:
The positions are for a PV who will be responsible for designing, implementing, and maintaining library characterization and validation software for use with standard cells, memory and macro blocks, and IO cells.
Requirements:
The candidates should have experiences in developing EDA software.
Must be proficient in C, C++, TCL, and development in Linux/Unix.
Knowledge on semiconductor device is strong plus.
Experience with SPICE or SPICE-like circuit simulation is important.
Knowledge of Verilog and VHDL is also highly desirable.
The ideal candidate would have a good understanding of library characterization, IP design, static timing analysis, power analysis, and signal integrity analysis flows.
Minimum Education Required / Minimum Experience Required : Master or Ph.D. in MS, EE, CS, Math or Physics
Senior Software Engineer for Fastspice Simulator (Location: BJ)
Position Description
Maintain and develop Cadence fastspice simulator.
Be responsible for writing specifications, designing and implementing product enhancements and fixes.
Needs to work with other global R&D teams..
Position Requirements
Education requirement: Master or Ph.D. in EE/CS/related research area.
Must be skilled in C/C++ programming, familiar with development under Linux/Unix environment.
Strong background in numerical computation and programming.
Knowledge of Analog Mixed-signal design and semiconductor device is a strong plus.
Good English communication skills both verbally and in writing.
Senior Software Engineer for RF simulator (Location: BJ)
Position Description:
Develop and maintain Cadence state-of-art RF simulation product
Be able to work with a cross-functional team to ensure the software is tested, integrated and documented.
Position Requirements:
Education Requirement: Master in EE, CS, or related.
Be proficient in C/C++ Unix development
Have a proven ability to learn from and work with an engineering and cross-functional team to deliver innovative products in a production environment.
Good command in written and oral English.
Experience in RF design is a plus.
Senior Software Engineer for Virtuoso ADE GXL (Location: BJ)
Position Description:
Dealing with manufacturing variation is becoming an increasingly important aspect of the custom digital and analog circuit design process. Virtuoso ADE GXL is a software tool for designers that offers statistical analysis, yield improvement, and design optimization capabilities to address this growing problem. We are seeing a talented software developer with a strong background in statistical analysis, data mining and modeling.
Position Requirements:
Strong background in statistical analysis, data mining, and modeling
Demonstrated proficiency in C++ and general software development skills
Master in Computer Science or Electrical Engineering required, PhD preferred.
Excellent communication skill in both mandarin and English.
Working knowledge of Matlab a plus.
Experience with Cadence Virtuoso or analog circuit design a plus.
Senior Software Engineer for Spice Simulator (Location: BJ)
Position Description
The position is for analog circuit simulation engineer responsible for designing, implementing and maintaining SPICE-like circuit simulation software for use with analog, RF and mixed signal circuit simulators. The engineer will be responsible for leading multiple development efforts through the development process, including writing specifications based on marketing and product requirements, designing and implementing product improvements and fixes, and working with a cross-functional team to ensure the software is tested, integrated and documented. The engineer must be proficient in C/C++ Unix development, and have a thorough knowledge of numerical methods for analog circuit simulation. The engineer must have a proven ability to learn from and work with an engineering and cross-functional team to deliver innovative products in a production environment.
Position Requirements
Well understanding on spice simulation technology, including MNA, Euler algorithm, dc, tran analyze method;
Well understanding on matrix solver & mathematic calculation;
Familiar with Spice, Spectre format & usage;
Skilled in C++ programming, familiar with development under Linux/Unix environment;
Be familiar with Analog-signal design is a plus;
Good English communication skill both verbally and writing;
Good problem solving skill and team work spirit;
Senior Software Engineer for AMS (Location: BJ)
Position Description:
Develop, enhance and maintain mixed signal circuit simulator which support Verilog-A, Verilog-AMS, VHDL-AMS in spice netlist, with some direction from manager or senior engineers
Position Requirements:
Familiar with Spice, Verilog, Verilog-A, Verilog-AMS, VHDL-AMS language
Analog circuit or digital simulator development experiences
Skilled in C++ programming, familiar with development under Linux/Unix environment.
Be familiar with Analog Mixed-signal design is a plus
EE or CS Master degree or above
Senior Software Engineer for Devices Compact Model (Location: BJ)
Position Description:
The position is for devices compact model engineer responsible for developing, implementing and maintaining device compact models in SPICE-like circuit simulation software. The engineer will be responsible for leading multiple development efforts through the development process, including writing specifications, designing and implementing product improvements and fixes. The engineer must have a proven ability to learn from work and work with a cross-functional team to deliver innovative products.
Position Requirements
Deep knowledge of Device Physics
Skilled in C/C++ programming, familiar with development under Linux/Unix environment;
Be familiar with numerical methods is a plus;
Be familiar with Analog-signal design is a plus;
Good English communication skill both verbally and writing;
Good problem solving skill and team work spirit;
Software Configuration Management (CM) Engineer (Location: BJ)
Position Description:
This position involves managing daily software build, test, and release processes, and configuration management support for R&D/PV/PE. The responsibility also includes maintaining and enhancing the existing automation systems, designing and developing new automation systems, software integration, and project management.
The candidate will also work closely with cross functional teams to diagnose and resolve problems.
Position Requirements:
MS in Computer Science or BS in Computer Science with Software Configuration Management, IT, or Software Engineering experience.
Familiar with Shell, Perl, and/or other programming languages.
Familiar with GNU Make, GCC/G++, and/or other compilers.
Experience of Unix/Linux system.
Good problem solving & analysis skills.
Good interpersonal, verbal, and written communication skills.
Fast and self learner.
IT background is welcomed.
Senior Software Engineer for Verilog-A simulator development(Location: BJ)
Position Description:
Develop, enhance and maintain Verilog-A simulator.
Requirements:
Familiar with Spice, Verilog-A, Verilog-AMS language
Skilled in C++ programming, familiar with development under Linux/Unix environment.
Analog circuit or digital simulator development experiences.
Well understanding on circuit simulation technology, including MNA, dc, tran method.
Good mathematic background & knowledge.
Be familiar with Analog Mixed-signal design is a plus
EE or CS Master degree of above